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NTE6810 Integrated Circuit 128 x 8-Bit Static Random Access Memory (SRAM)
Description: The NTE6810 is a byte-orgainzed memory in a 24-Lead DIP type package designed for use in bus- organized systems. It is fabricated with N-channel silicon-gate technology. For ease of use, this device operates from a single power supply, has compatibility with TTL and DTL, and needs no clocks or refreshing because of static operation. The memory is compatible with the 6800 Microcomputer Family, providing random storage in byte increments. Memory expansion is provided through multiple Chip Select inputs. Features: D Organized as 128 Bytes of 8-Bits D Static Operation D Bidirectional Three-State Data Input/Output D Six Chip Select Inputs (Four Active Low, Two Active High) D Single 5V Power Supply D TTL Compatible D Maximum Access Time: 450ns Absolute Maximum Ratings: Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Input Voltage, Vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Thermal Resistance, Junction to Ambient, RJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +120C/W Note 1. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage (e.g., either VSS or VCC).
DC Electrical Characteristics: (VCC = 5V 5%, VSS = 0, TA = 0 to +70C unless otherwise specified)
Parameter Input High Voltage Input Low Voltage Input Current (An, R/W, CSn) Output High Voltage Output Low Voltage Output Leakage Current (Three-State) Supply Current Input Capacitance (An, R/W, CSn, CSn) Output Capacitance (Dn) Symbol VIH VIL Iin VOH VOL ITSI ICC Cin Cout Vin = 0 to 5.25V IOH = -205A IOL = 1.6mA CS = 0.8V or CS = 2V, Vout = 0.4V to 2.4V VCC = 5.25V, All other pins grounded Vin = 0, TA = +25C, f = 1MHz Vout = 0, TA = +25C, f = 1MHz, CSO = 0 Test Conditions Min VSS +2.0 - 2.4 - - - - - Max VCC 2.5 - 0.4 10 80 7.5 12.5 Unit V V A V V A mA pF pF
VSS -0.3 VSS +0.8
AC Operating Conditions and Characteristics:
Parameter Read Cycle Time Access Time Address Setup Time Address Hold Time Data Delay Time (Read) Read to Select Delay Time Data Hold from Address Output Hold Time Data Hold from Read Read Hold from Chip Select Write Cycle Time Address Setup Time Address Hold Time Chip Select Pulse Width Write to Chip Select Delay Time Data Setup Time (Write) Input Hold Time Write Hold Time from Chip Select Symbol tcyc(R) tacc tAS tAH tDDR tRCS tDHA tH tDHR tRH tcyc(W) tAS tAH tCS tWCS tDSW tH tWH Min 450 - 20 0 - 0 10 10 10 0 450 20 0 300 0 190 10 0 Max - 450 - - 230 - - - 80 - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read Cycle (VCC = 5V 5%, VSS = 0, TA = 0 to +70 unless otherwise specified)
Write Cycle (VCC = 5V 5%, VSS = 0, TA = 0 to +70 unless otherwise specified)
Read Cycle Timing
tcyc(R) tacc Address tAS CS tDDR CS tRH tAH
tRCS R/W
tDHA tDHR tH Data In Data Valid
= Don't Care
Note 1. Voltage levels shown are VL 0.4V, VH 2.4V, unless otherwise specified. Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified. Note 3. CS and CS have same timing. Write Cycle Timing
tcyc(W) Address tAS CS tCS tAH
CS tWCS R/W tDSW Data In Data in Stable tH tWH
= Don't Care
Note 1. Voltage levels shown are VL 0.4V, VH 2.4V, unless otherwise specified. Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified. Note 3. CS and CS have same timing.
Pin Connection Diagram
GND D0 D1 D2 D3 D4 D5 D6 D7
1 2 3 4 5 6 7 8 9
24 VCC 23 A0 22 A1 21 A2 20 A3 19 A4 18 A5 17 A6 16 R/W 15 CS5 14 CS4 13 CS3
CS0 10 CS1 CS2 11 12
24
13
1
12
1.300 (33.02) Max .225 (5.73) Max
.520 (13.2)
.100 (2.54) 1.100 (27.94)
.126 (3.22) Min
.600 (15.24)

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